According to a formula derived by experience, the signal delay will be 5 ns per meter. In this case, the coaxial cable length is 50 cm, and the length of the parallel datapath is around 40 cm. The Clk_out that triggers the input data will be routed to a data-source board as the system clock by a coaxial cable ( Fig. Then the output clock, Clk_out, will be 155 MHz, only one-eighth of the input clock. ![]() Suppose the frequency of the input clock, Clk_in, is 1.25 GHz. Let's take an example of an 8:1 multiplexer. This causes a tough synchronization problem. ![]() Therefore, the parallel data input is well synchronized with the multiplexer as long as the data source is very close to it.īut in some applications, the multiplexer will probably be a bit far from the data source (e.g., they're on different pc boards). A low-frequency clock is derived from the Clk_in by the internal clock circuitry as an output clock (Clk_out) that can be used to trigger the parallel data input. ![]() The multiplexer takes a high-frequency clock as the system input clock (Clk_in) that's synchronized with the serial output data. Multiplexers are widely used in communication systems to convert parallel signals into serial signals.
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